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| TECHNICAL DATA IN74LV574 Octal D-type flip-flop; positive edge-trigger (3-State) The 74LV574 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT574. The 74LV574 is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOWto-HIGH CP transition. When OE is LOW, the contents of the eight flipflops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. * Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS * Supply voltage range: 1.0 to 5.5 V * Low input current: 1.0 A; 0.1 A at O = 25 N * High Noise Immunity Characteristic of CMOS Devices N SUFFIX PLASTIC DIP 20 1 20 1 DW SUFFIX SO ORDERING INFORMATION IN74LV574N IN74LV574DW IZ74LV574 Plastic DIP SOIC chip TA = -40 to 125 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Output Enable PIN 20=VCC PIN 10 = GND L L L H L,H, X Clock D H L X X Output Q H L no change Z H= high level L = low level X = don't care Z = high impedance INTEGRAL 1 IN74LV574 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage Input diode current Output diode current Output source or sink current VCC current GND current Power dissipation per package: Plastic DIP * 4 SO * 4 Storage Temperature Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds Value -0.5 to +7.0 20 50 35 70 70 750 500 -65 to +150 260 Unit V mA mA mA mA mA mW IOK * IO * ICC IGND PD 3 Tstg TL * C C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. * 1 VI < -0.5 V or VI > VCC + 0.5 V. * 2 VO < -0.5 V or VO > VCC + 0.5 V. * 3 -0.5 V < VO < VCC + 0.5 V. * 4 Derating - Plastic DIP: - 12 mW/C from 70 to 125C SO Package: : - 8 mW/C from 70 to 125C RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO TA tr, t f DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) 0 V VCC 2.0 V 2.0 V VCC 2.7 V 2.7 V VCC 3.6 V 3.6 V VCC 5.5 V Parameter Min 1.0 0 0 -40 0 0 0 0 Max 5.5 VCC VCC +125 500 200 100 50 Unit V V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74LV574 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Symbol Parameter conditions VCC V 25C min VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 5.5 2.7 3.6 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 Guaranteed Limit -40C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 0.1 8.0 0.2 85C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 1.0 20 0.5 125C min 0.9 1.4 2.0 2.0 2.0 3.15 3.85 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 max 0.3 0.6 0.8 0.8 0.8 1.35 1.65 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 1.0 160 0.85 V Unit VIL LOW level output voltage V VOH HIGH level VI = VIH or VIL output IO = -100 A voltage V VI = VIH or VIL IO = -8 mA VI = VIH or VIL IO = -16 mA VOL LOW level VI = VIH or VIL output IO = 100 A voltage V V V VI = VIH or VIL IO = 8 mA VI = VIH or VIL IO = 16 mA II ICC ICC1 Input current Supply current VI = VCC or 0 V VI =VCC or 0 V IO = 0 A V V A A mA Additional VI = VCC - 0.6V supply current per input INTEGRAL 3 IN74LV574 0.5 0.5 5 10 A IOZ Three state 3-state output leakage VI (11) = VIH current VO =VCC or 0 V 5.5 - - - - AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t r=t f=2.5 ns) Test Symbol Parameter conditions VCC V -40C to 25C min tPHL, tPLH Propagation delay , Clock to Q VI = 0 V or V1 Figures 1,3 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 5.5 VI = 0 V or VCC 5.5 max 160 26 20 16 14 160 31 23 20 17 140 26 20 16 14 7.0* 50* Guaranteed Limit 85C min max 170 34 25 20 17 170 39 29 24 20 160 34 25 20 17 125C min max 200 43 31 25 21 200 48 36 29 24 180 43 31 25 21 ns Unit tPHZ, tPLZ Propagation delay, OE to Q VI = 0 V or V1 Figures 2,4 ns tPZH, tPZL Propagation delay, OE to Q VI = 0 V or V1 Figures 2,4 ns CI CPD * T = 25oC Input capacitance Power dissipation capacitance (per flip-flop) pF pF TEST POINT TEST POINT 1k CL * DEVICE UNDER TEST OUTPUT * CL DEVICE UNDER TEST OUTPUT Connect to VCC when testing tPLZ and tPZL Connect to GND when testing tPHZ and t PZH * Includes all probe and jig capacitance Figure 1. Test Circuit * Includes all probe and jig capacitance Figure 2. Test Circuit TIMING REQUIREMENTS(CL=50 pF, t r=t f=2.5 ns) INTEGRAL 4 IN74LV574 Test Symbol Parameter conditions VCC V -40C to 25C min max 2 17 21 27 31 Guaranteed Limit 85C min 34 25 20 max 125C min 41 30 24 max ns ns 22 16 13 5 5 5 5 15 19 24 26 19 15 5 5 5 5 12 16 20 ns Unit tw Pulse Width, Clock (high) VI = 0 V or V1 Figures 1,3 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 1.2 2.0 2.7 3.0 4.5 120 29 21 17 15 40 19 14 11 9 5 5 5 5 - tsu Setup Time, Data to Clock VI = 0 V or V1 Figures 1,5 th Hold Time, Clock to Data VI = 0 V or V1 Figures 1,5 fc Clock Frequency VI = 0 V or V1 Figures 1,3 MHz VOL and VOH are the typical output voltage drop that occur with the output load. Figure 3. Switching Waveforms INTEGRAL 5 IN74LV574 Figure 4. Switching Waveforms Figure 5. Switching Waveforms Temperature, C Symbol ,V INTEGRAL 6 IN74LV574 -40C to 25 85 Level of a signal 125 V % 50 50 56 56 50 50 50 58 52 50 12 11 12 11 12 88 88 87.5 88 88 V 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.6 0.65 0.90 0.78 1.4 2.0 2.2 3.35 % 50 50 56 56 50 50 50 60 53 50 12.5 11 12.5 11 12 86.5 87.5 87 88 88 V 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.37 0.45 0.65 0.7 1.0 0.68 1.3 1.9 2.1 3.25 % 50 50 56 56 50 50 50 62 55 50 12.5 11 12.7 11.5 11 85 86.5 86 87.5 88 V1 VM INPUTS VM OUTPUTS VX VY 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 1.2 2.0 2.7 3.0 4.5 0.6 1.0 1.5 1.5 2.25 0.6 1.0 1.5 1.5 2.25 0.32 0.4 0.55 0.6 0.85 0.88 1.5 2.1 2.3 3.45 EXPANDED LOGIC DIAGRAM CHIP PAD DIAGRAM INTEGRAL 7 IN74LV574 Chip marking EALV574 18 19 1.51 + 0.03 20 17 16 15 14 13 12 11 10 01 02 03 Y 09 04 05 06 07 08 (0,0) 1.9 + 0.03 X Location of marking (mm): left lower corner x=1.656, y=1.353. Chip thickness: 0.46 0.02 mm, (0.35 0.02 mm - for SOIC). PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 Symbol Output enable D0 D1 D2 D3 D4 D5 D6 D7 GND Clock Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 VCC Location (left lower corner), mm X 0.128 0.128 0.330 0.576 0.738 1.054 1.216 1.466 1.682 1.682 1.682 1.682 1.422 1.149 0.971 0.811 0.633 0.360 0.128 0.128 Y 0.545 0.229 0.120 0.120 0.120 0.120 0.120 0.120 0.314 0.533 0.839 1.108 1.274 1.274 1.274 1.274 1.274 1.274 1.108 0.854 Pad size, mm 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 0.108 x 0.108 Note: Pad location is given as per metallization layer INTEGRAL 8 |
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